average supply current for dram operation pre t clk  = min, (4 mclk cycles) 55 40 ma i cc average supply current for dram operation dup t clk  = min, (8 mclk cycles) 55 40 ma i cc average supply current for dram operation rdb t clk  = min, (2 or 3 mclk cycles) 160 130 ma i cc average supply current for dram operation uwb t clk  = min, (2 or 3 mclk cycles) 160 130 ma i cc average supply current for dram operation vdx  t clk  = min, (4 mclk cycles) 80 60 ma i cc average supply current for video output t vclk  = min 70 70 ma

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 109 7 electrical speci?ations ac specifications every ac timing parameter is illustrated in at least  one of the timing figures in chapter 8. the ?efer? column in each timing table refers to the exact  measurement levels illustrated in figures 7.3  through 7.6. pixel alu timing parameters the timing parameters of M5M410092B-10 and  -12 are presented in table 7.4. table 7.4  pixel alu timing parameters  symbol parameter M5M410092B unit refer ch. 8 figure -10a -10 -12 min max min max min max t clk master clock mclk  cycle time 10 16000 10  [ 16000 12 16000 ns t 1 4 t clkh mclk high pulse  width 4?  5 nst 2 4 t clkl mclk low pulse  width 4?  5 nst 3 4 t rss reset  setup time 0? 0 nst 6 1 t rsp reset  pulse width 40  40  48  ns t 7 2 t ens palu_en setup  time 3? 4 nst 8 4 t enh palu_en hold  time 1.5  1.5  1.5  ns t 9 4 t ops palu_op setup  time 3? 4 nst 8 4 t oph palu_op hold  time 1.5  1.5  1.5  ns t 9 4 t ads palu_a setup time 3? 4 nst 8 4 t adh palu_a hold time 1.5  1.5  1.5  ns t 9 4 t dqs palu_dq,  palu_dx setup  time 3? 4 nst 8 5 t dqh palu_dq,  palu_dx hold  time 1.5  1.5  1.5  ns t 9 5 t wes palu_we setup  time 3? 4 nst 8 4 t weh palu_we hold  time 1.5  1.5  1.5  ns t 9 4 [  t clk  = 10.0 ns except that for the alpha saturate logic t clk  = 12.0 ns.

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 110 7 electrical speci?ations t bes palu_be setup  time 3? 4 nst 8 4 t beh palu_be hold  time 1.5  1.5  1.5  ns t 9 4 t clz mclk to  palu_dq low     impedance 4? 5 nst 10 4 t cq palu_dq access  time ?4?4  18nst 11 4 t cvd palu_dq data val- id time 4? 4 nst 12 4 t chz mclk to  palu_dq high  im- pedance ??  4nst 13 4 t pss pass_in setup  time 2? 3 nst 8 5 t psh pass_in hold time 0? 0 nst 9 5 t cps mclk to valid  pass_out ??  8nst 11 5 t cpsv pass_out data  valid time 3? 3 nst 12 5 t cht mclk to valid hit  ?5?5  35nst 11 6 symbol parameter M5M410092B unit refer ch. 8 figure -10a -10 -12 min max min max min max table 7.4  pixel alu timing parameters (con?.)

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 111 7 electrical speci?ations dram timing parameters the measurements of the dram interlock timings  in tables 7.6 and 7.7 are from the mclk rising  edge of the first operation to the mclk rising  edge of the second operation. both mclk edges  are measured at 1.5 v. table 7.5  minimum requirements of the dram timing parameters symbol parameter M5M410092B unit refer ch. 8 figure -10a, -10 -12 t ref refresh interval for array 17 17 ms   t dens dram_en setup time 3 4 ns t 8 7 t denh dram_en hold time 1.5 1.5 ns t 9 7 t dops dram_op setup time 3 4 ns t 8 7 t doph dram_op hold time 1.5 1.5 ns t 9 7 t dbks dram_bs setup time 3 4 ns t 8 7 t dbkh dram_bs hold time 1.5 1.5 ns t 9 7 t dads dram_a setup time 3 4 ns t 8 7 t dadh dram_a hold time 1.5 1.5 ns t 9 7

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 112 7 electrical speci?ations table 7.6  minimum requirements of the dram interlock timings for operations on same bank  a. the maximum timing limit from acp to pre is 100,000 ns. b. the operation from pre to acp requires at least two clock cycles. at the ?st clock  rising edge, pre starts. at the second clock rising edge, the preparation for acp starts. symbol parameter M5M410092B unit ch. 8 timing  figure -10a, -10 -12 t dabs access page to block transfer 36 36 ns 7 t daps a access page to precharge bank 60 72 ns 7 t dads access page to duplicate page 48 48 ns 8 t davs access page to video transfer 40 48 ns 9 t dbbs block transfer to block transfer 20 24 ns 7 t dbps block transfer to precharge bank 20 24 ns 7 t dbds block transfer to duplicate page 20 24 ns 8 t dbvs block transfer to video transfer 20 24 ns 10 t dpas b precharge bank to access page 40 48 ns 7 t dpps precharge bank to precharge bank 10 12 ns 10 t ddbs duplicate page to block transfer 80 96 ns 8 t ddps duplicate page to precharge bank 80 96 ns 9 t ddds duplicate page to duplicate page 80 96 ns 8 t ddvs duplicate page to video transfer 80 96 ns 9 t dvbs video transfer to block transfer 40 48 ns 10 t dvps video transfer to precharge bank 20 24 ns 9 t dvds video transfer to duplicate page 40 48 ns 9 t dvvs video transfer to video transfer 80 96 ns 9

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 113 7 electrical speci?ations    symbol parameter M5M410092B unit ch. 8 timing figure -10a, -10 -12 t daad access page to access page 40 48 ns 11 t dabd access page to block transfer 10 12 ns 11 t dapd access page to precharge bank 40 48 ns 11 t dadd access page to duplicate page 40 48 ns 12 t davd access page to video transfer 40 48 ns 13 t dbad block transfer to access page 10 12 ns 11 t dbbd block transfer to block transfer 20 24 ns 11 t dbpd block transfer to precharge bank 10 12 ns 11 t dbdd block transfer to duplicate page 10 12 ns 11 t dbvd block transfer to video transfer 10 12 ns 13 t dpad precharge bank to access page 10 12 ns 11 t dpbd precharge bank to block transfer 10 12 ns 11 t dppd precharge bank to precharge bank 10 12 ns 11 t dpdd precharge bank to duplicate page 10 12 ns 11 t dpvd precharge bank to video transfer 10 12 ns 13 t ddad duplicate page to access page 80 96 ns 12 t ddbd duplicate page to block transfer 10 12 ns 12 t ddpd duplicate page to precharge bank 40 48 ns 12 t dddd duplicate page to duplicate page 80 96 ns 12 t ddvd duplicate page to video transfer 80 96 ns 13 t dvad video transfer to access page 40 48 ns 13 t dvbd video transfer to block transfer 10 12 ns 13 t dvpd video transfer to precharge bank 20 24 ns 13 t dvdd video transfer to duplicate page 40 48 ns 13 t dvvd video transfer to video transfer 80 96 ns 13

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 114 7 electrical speci?ations video buffer timing parameters table 7.7  video buffer timing parameters symbol parameter M5M410092B unit refer ch. 8 figure -10a, -10 -12 min max min max t vclk vid_clk cycle time 12  12  ns t 1 14 t vclkh vid_clk high pulse width 5  5  ns t 2 14 t vclkl vid_clk low pulse width 5  5  ns t 3 14 t vces vid_cke setup time 4  4  ns t 8 14 t vceh vid_cke hold time 0  0  ns t 9 14 t vq vid_q access time from vid_clk  8  8 ns t 11 14 t vqvc vid_q valid after vid_clk 3  3  ns t 12 14 t vlz vid_q output low impedance 3  3  ns t 16 14 t vhz vid_q output high impedance  3  3 ns t 15 14 t vqe vid_q access time from vid_oe high  9  9 ns t 17 14 t vqve vid_q valid after vid_oe low     ns t 14 14 t vxci1 initial vdx after last internal vid_clk 14  14  ns  15 t vxci2 initial vdx before next internal vid_clk 80  80  ns  15 t vxqfi vid_qsf delay time after initial vdx  80  80 ns t 11 15 t qsf vid_qsf delay time from internal vid_clk 38  25  25 ns t 11 16 t vxc1 normal vdx after internal vid_clk 38 20  20  ns  16 t vxc2 normal vdx before next internal vid_clk 38 60  60  ns  16

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 115 7 electrical speci?ations boundary-scan timing parameters table 7.8  boundary-scan timing parameters symbol parameter M5M410092B -10a, -10, -12 unit refer ch. 8 figure min max t sclk scan_tck cycle time 100  ns t 1 17 t sclkh scan_tck high pulse width 40  ns t 2 17 t sclkl scan_tck low pulse width 40  ns t 3 17 t scnts scan_tms setup time  8  ns t 8 17 t scnth scan_tms hold time 26  ns t 9 17 t scnis scan_tdi setup time 8  ns t 8 17 t scnih scan_tdi hold time 26  ns t 9 17 t slz scan_tck to scan_tdo low impedance  20 ns t 18 17 t sq scan_tdo access time  26 ns t 19 17 t svd scan_tdo data valid time 8  ns t 20 17 t shz scan_tck to scan_tdo high impedance  20 ns t 21 17 t scnrs scan_rst  setup time 8  ns t 6 18 t scnrp scan_rst  pulse width 30  ns t 7 18

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 116 7 electrical speci?ations

 timing diagrams 8



 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 117 8 timing diagrams timing diagrams this chapter shows 18 timing diagrams, which are  summarized in table 8.1. these diagrams show  the gross timing specifications. refer to chapter 7  for exact timing measurements. also, the entries  of parameter values from tables 7.4 through 7.9  are repeated here for convenient reference.    table 8.1 timing diagram figures figure description 8.1 power on reset 8.2 restart reset 8.3 dram array initialization 8.4 pixel port read 8.5 pixel port write 8.6 pick logic timing 8.7 dram operations on the same bank (1) 8.8 dram operations on the same bank (2) 8.9 dram operations on the same bank (3) 8.10 dram operations on the same bank (4) 8.11 dram operations between two different banks (1) 8.12 dram operations between two different banks (2) 8.13 dram operations between two different banks (3) 8.14 internal vid_clk and video output timing 8.15 video output sequence from initial vdx for normal and reversed modes 8.16 continuous video output sequence in normal mode during display 8.17 boundary scan 8.18 boundary scan reset

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 118 8 timing diagrams           figure 8.1  power on reset          figure 8.2  restart reset        mclk > 500? > 9 cycles reset internal function v dd t rss stabilize internal power supply reset registers initialize dram array start normal operation m1020 mclk > 9 cycles reset internal function t rss reset registers initialize dram array start normal operation t rss t rsp m1021 table 8.2 reset timing parameters symbol parameter M5M410092B unit refer -10a, -10 -12 min max min max t rss reset  setup time 0  0  ns t 6 t rsp reset  pulse width 40  48  ns t 7

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 119 8 timing diagrams        figure 8.3  dram array initialization   mclk dram_op dram_bs internal function acp acp acp acp pre pre pre pre abcdac bd initialize dram array start normal operation mclk dram_op dram_bs internal function acp pre acp acp pre acp pre pre aab c bd cd initialize dram array start normal operation or m1019

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 120 8 timing diagrams              note:  refer to figure 2.6 for an example of combined operations of pixel alu read and write. figure 8.4  pixel port read           figure 8.5    pixel port write m1018 t ens palu_dq [8n+7..8n] t enh t oph t ops t weh t wes t adh t ads t beh t bes t clz t cq t cvd t cq t clk t clkh t clkl 111 000 000111 block : word valid id valid data palu_be n palu_a palu_we palu_op palu_en mclk t chz mclk 1 23456789 10 111 100 101 010 or 011 000 or 001 register block:xxx block:xxx block:word reg data dirty tag dirty tag new data new data reg data new data new data pass_in palu_en palu_op palu_we palu_a palu_be n palu_dq [8n+7..n] palu_dx n pass_in pass_out t dqs t dqh t pss t psh t cps t cpsv m1017

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 121 8 timing diagrams         table 8.3 pixel alu timing parameters  symbol parameter M5M410092B unit refer -10a -10 -12 min max min max min max t clk master clock mclk cycle time 10 16000 10  [ 16000 12 16000 ns t 1 t clkh mclk high pulse width 4  4  5  ns t 2 t clkl mclk low pulse width 4  4  5  ns t 3 t ens palu_en setup time 3  3  4  ns t 8 t enh palu_en hold time 1.5  1.5  1.5  ns t 9 t ops palu_op setup time 3  3  4  ns t 8 t oph palu_op hold time 1.5  1.5  1.5  ns t 9 t ads palu_a setup time 3  3  4  ns t 8 t adh palu_a hold time 1.5  1.5  1.5  ns t 9 t wes palu_we setup time 3  3  4  ns t 8 t weh palu_we hold time 1.5  1.5  1.5  ns t 9 t bes palu_be setup time 3  3  4  ns t 8 t beh palu_be hold time 1.5  1.5  1.5  ns t 9 t clz mclk to palu_dq low imped- ance 4 4 ?nst 10 t cq palu_dq access time  14  14  18 ns t 11 t cvd palu_dq data valid time 4  4  4  ns t 12 t chz mclk to palu_dq high  imped- ance ?  4?nst 13 t dqs palu_dq, palu_dx setup time 3  3  4  ns t 8 t dqh palu_dq, palu_dx hold time 1.5  1.5  1.5  ns t 9 t pss pass_in setup time 2  2  3  ns t 8 t psh pass_in hold time 1.5  1.5  1.5  ns t 9 t cps mclk to valid pass_out  6  6  8 ns t 11 t cpsv pass_out data valid time 3  3  3  ns t 12 [  t clk  = 10.0 ns except that for the alpha saturate logic t clk  = 12.0 ns.

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 122 8 timing diagrams note: 1. the hit signal is cleared by writing to the compare control register. 2. the hit signal can be set by the comparison result from the pass_in and pass_out pins, which are generated two cycles  before the hit signal is. figure 8.6  picking logic timing        table 8.4 picking logic timing parameter symbol parameter M5M410092B unit refer -10a, -10 -12 min max min max t cht mclk to valid hit   35  35 ns t 11 mclk 1 23456789 10 111 011 palu_en palu_op palu_we palu_a palu_be [2..0] palu_be 3 palu_dq [31..0] pass_in pass_out t cht 000101 block:word xexxxxxx data hit t cht note 1 note 2 m1016

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 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 124 8 timing diagrams             note:   bkx means any block transfer operation, such as uwb, mwb, or rdb. figure 8.7  dram operations on the same bank (1)       note:   bkx means any block transfer operation, such as uwb, mwb, or rdb. figure 8.8  dram operations on the same bank (2) mclk pre dram_en dram_op dram_bs dram_a t doph nop acp nop bkx nop bkx nop pre a aaaa page block block page t dops t dens t dbkh t dbks t dadh t dads t dpas t dabs t dbbs t dbps t denh page m1015 mclk pre dram_en dram_op dram_bs dram_a nop acp nop bkx nop bkx nop pre a aaaa page block block page t daps page m1043 mclk acp dram_en dram_op dram_bs dram_a nop dup nop dup nop bkx nop dup a aaaa page page block page t dads t ddds t ddbs t dbds page m1014

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 125 8 timing diagrams                 a. the maximum timing limit from acp to pre is 100,000 ns. b. the operation from pre to acp requires at least two clock cycles. at the ?st clock  rising edge, pre starts. at the second clock rising edge, the preparation for acp  starts. table 8.5 minimum requiremens of the dram port interface timing parameters symbol parameter M5M410092B unit refer timing figure -10a, -10 -12 t dens dram_en setup time 3 4 ns t 8 8.7 t denh dram_en hold time 1.5 1.5 ns t 9 8.7 t dops dram_op setup time 3 4 ns t 8 8.7 t doph dram_op hold time 1.5 1.5 ns t 9 8.7 t dbks dram_bs setup time 3 4 ns t 8 8.7 t dbkh dram_bs hold time 1.5 1.5 ns t 9 8.7 t dads dram_a setup time 3 4 ns t 8 8.7 t dadh dram_a hold time 1.5 1.5 ns t 9 8.7 table 8.6 minimum requirements of the dram interlock timings for operations on same bank symbol parameter M5M410092B unit timing  figure -10a, -10 -12 t dabs access page to block transfer 36 36 ns 8.7 t daps a access page to precharge bank 60 72 ns 8.7 t dads access page to duplicate page 48 48 ns 8.8 t dbbs block transfer to block transfer 20 24 ns 8.7 t dbps block transfer to precharge bank 20 24 ns 8.7 t dbds block transfer to duplicate page 20 24 ns 8.8 t dpas b precharge bank to access page 40 48 ns 8.7 t ddbs duplicate page to block transfer 80 96 ns 8.8 t ddds duplicate page to duplicate page 80 96 ns 8.8

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 126 8 timing diagrams             figure 8.9   dram operations on the same bank (3) note:   bkx means any  block transfer operation, such as uwb, mwb, or rdb. figure 8.10  dram operations on the same bank (4) mclk acp dram_en dram_op dram_bs dram_a nop vdx nop dup vdx nop pre a aaaa page page line page t davs t dvds t ddvs t dvps line m1013 mclk acp dram_en dram_op dram_bs dram_a nop vdx nop dup vdx nop pre a aaaa page page line page t dvvs line t ddps m1044 mclk vdx dram_en dram_op dram_bs dram_a nop bkx nop vdx nop pre nop pre a aaaa line line page page t dvbs t dbvs t dpps block m1012

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 127 8 timing diagrams         table 8.7 minimum requirements of the dram interlock timings for operations on same bank symbol parameter M5M410092B unit timing  figure -10a, -10 -12 t davs access page to video transfer 40 48 ns 8.9 t dbvs block transfer to video transfer 20 24 ns 8.10 t dpps precharge bank to precharge bank 10 12 ns 8.10 t ddps duplicate page to precharge bank 80 96 ns 8.9 t ddvs duplicate page to video transfer 80 96 ns 8.9 t dvbs video transfer to block transfer 40 48 ns 8.10 t dvps video transfer to precharge bank 20 24 ns 8.9 t dvds video transfer to duplicate page 40 48 ns 8.9 t dvvs video transfer to video transfer 80 96 ns 8.9

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 128 8 timing diagrams            note:   bkx means any  block transfer operation, such as uwb, mwb, or rdb. figure 8.11  dram operations between two different banks (1) figure 8.12  dram operations between two different banks (2) mclk pre dram_en dram_op dram_bs dram_a pre acp bkx nop bkx pre ac cd page block page t dbad t dbpd page dup b page acp bdb page page block t dppd t dpad t dabd t dpdd t dbbd m1011 mclk pre dram_en dram_op dram_bs dram_a pre acp bkx nop bkx pre ac cd page block page t dbdd page dup b page acp bdb page page block t dpbd t daad t dapd m1045 mclk acp dram_en dram_op dram_bs dram_a dup dup pre acp a bcad page page page page t dadd t ddbd t ddpd page bkx a block t dddd t ddad m1010

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 129 8 timing diagrams         table 8.8 minimum requirement of the dram interlock timings for operations between two  different banks symbol parameter M5M410092B unit timing figure -10a, -10 -12 t daad access page to access page 40 48 ns 8.11 t dabd access page to block transfer 10 12 ns 8.11 t dapd access page to precharge bank 40 48 ns 8.11 t dadd access page to duplicate page 40 48 ns 8.12 t dbad block transfer to access page 10 12 ns 8.11 t dbbd block transfer to block transfer 20 24 ns 8.11 t dbpd block transfer to precharge bank 10 12 ns 8.11 t dbdd block transfer to duplicate page 10 12 ns 8.11 t dpad precharge bank to access page 10 12 ns 8.11 t dpbd precharge bank to block transfer 10 12 ns 8.11 t dppd precharge bank to precharge bank 10 12 ns 8.11 t dpdd precharge bank to duplicate page 10 12 ns 8.11 t ddad duplicate page to access page 80 96 ns 8.12 t ddbd duplicate page to block transfer 10 12 ns 8.12 t ddpd duplicate page to precharge bank 40 48 ns 8.12 t dddd duplicate page to duplicate page 80 96 ns 8.12

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 130 8 timing diagrams        figure 8.13  dram operations between two different banks (3) mclk dup dram_en dram_op dram_bs dram_a bkx vdx bkx nop acp dup ac da page page page t davd line vdx c line vdx bbb block line block t dbvd t dvbd t dvdd t dvvd pre d page t dpvd t dvad t dvpd t ddvd m1009 table 8.9 minimum requirement of the dram interlock timings for operations between two  different banks symbol parameter M5M410092B unit -10a, -10 -12 t davd access page to video transfer 40 48 ns t dbvd block transfer to video transfer 10 12 ns t dpvd precharge bank to video transfer 10 12 ns t ddvd duplicate page to video transfer 80 96 ns t dvad video transfer to access page 40 48 ns t dvbd video transfer to block transfer 10 12 ns t dvpd video transfer to precharge bank 20 24 ns t dvdd video transfer to duplicate page 40 48 ns t dvvd video transfer to video transfer 80 96 ns

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 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 132 8 timing diagrams        note: 1. the deassertion of vid_cke at the current vid_clk rising edge will mask out the next internal vid_clk cycle. 2. timings are measured from the vid_clk pin or from the vid_oe pin. figure 8.14  internal vid_clk and video output timing       note: 1. note that the vid_oe is always ??for video output enable is assumed. 2. timings are measured from the mclk pin or from the vid_clk pin. figure 8.15  video output sequence from intial vdx for normal and reversed modes         vid_clk vid_cke vid_clk vid_oe vid_q data 1 data 3 data 4 data 5 data 2 data 2 t vclk t vq t vclkh t vclkl data 6 t vqe t vlz t vhz internal t vceh 1 1 t vces t vqvc t vqve m1006 internal vid_clk data 0 vid_q normal mode vid_qsf data 1 data 2 data 3 mclk dram_op dram_a [8..7] vdx 10 m1024 data 1 vid_q reversed mode data 0 data 3 data 2 t vq t vxqfi t vxci1 t vxci2 vid_clk vid_cke

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 133 8 timing diagrams table 8.10   video buffer timing parameters symbol parameter M5M410092B unit refer timing figure -10a, -10 -12 min max min max t vclk vid_clk cycle time 12  12  ns t 1 8.14 t vclkh vid_clk high pulse width 5?ns t 2 8.14 t vclkl vid_clk low pulse width 5?ns t 3 8.14 t vces vid_cke setup time 4?ns t 8 8.14 t vceh vid_cke hold time 0?ns t 9 8.14 t vq vid_q access time from vid_clk ??nst 11 8.14 t vqvc vid_q valid after vid_clk 3?nst 12 8.14 t vlz vid_q output low impedance 3?nst 16 8.14 t vhz vid_q output high impedance ??nst 15 8.14 t vqe vid_q access time from vid_oe high ??nst 17 8.14 t vqve vid_q valid after vid_oe low ns t 14 8.14 t vxci1 initial vdx after last internal vid_clk 14  14  ns  8.15 t vxci2 initial vdx before next internal vid_clk 80  80  ns  8.15 t vxqfi vid_qsf delay time after initial vdx  80  80 ns t 11 8.15

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 134 8 timing diagrams      note: 1. t vxc1  specifies the earliest allowed normal vdx. 2. t vxc2  specifies the latest allowed normal vdx. figure 8.16  continuous video output sequence in normal mode during display         vid_clk vid_q  [15 . . 0] vid_qsf mclk dram_op vdx dram_a  [8 . . 7] 1 0 373839 0 1 373839 0 1 dram_bs 0 vdx 1 vdx 2 m1022 0 1 2 37 38 39 0 1 2 38 0x 10 0x 39012 bank 0 bank 1 bank 2 t qsf t qsf t vq t vxc1 t vxc2 initial vdx during retrace normal vdx during retrace normal vdx during display vid_cke table 8.11  video buffer timing parameters symbol parameter M5M410092B unit refer -10a, -10 -12 min max min max t qsf vid_qsf delay time from internal vid_clk 38  25  25 ns t 11 t vxc1 normal vdx after internal vid_clk 38 20  20  ns  t vxc2 normal vdx before next internal vid_clk 38 60  60  ns 

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 135 8 timing diagrams       figure 8.17  boundary scan         scan_tck controller state scan_tms t sclkh t sclk test-logic reset run-test-idle shift-ir shift-ir exit-ir update-ir scan_tdi t sclkl t scnts t scnth t scnis t sq t shz t slz t svd scan_tdo t scnih note 1 m1004 table 8.12  boundary-scan timing parameters symbol parameter M5M410092B -10a, -10, -12 unit refer min max t sclk scan_tck cycle time 100  ns t 1 t sclkh scan_tck high pulse width 40  ns t 2 t sclkl scan_tck low pulse width 40  ns t 3 t scnts scan_tms setup time  8  ns t 8 t scnth scan_tms hold time 26  ns t 9 t scnis scan_tdi setup time 8  ns t 8 t scnih scan_tdi hold time 26  ns t 9 t slz scan_tck to scan_tdo low impedance  20 ns t 18 t sq scan_tdo access time  26 ns t 19 t svd scan_tdo data valid time 8  ns t 20 t shz scan_tck to scan_tdo high impedance  20 ns t 21

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 136 8 timing diagrams figure 8.18  boundary scan reset       scan_rst scan_tck t scnrs t scnrp m1005 table 8.13  boundary-scan reset timing parameters symbol parameter M5M410092B -10a, -10, -12 unit refer min max t scnrs scan_rst  setup time 8  ns t 6 t scnrp scan_rst  pulse width 30  ns t 7

 packaging 9



 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 137 9 packaging packaging the 3d-ram is housed in 128-pin qfp(fp) and  reverse qfp(rf) packages. for the purpose of convenient reference, the  pinout diagrams for the 3d-ram are repeated on  pages 137 and 138.  page 103 contains the mechanical specification  for the fp and rf packages. the thermal characteristics data for both  packages is on page 142. 3d-ram pinouts there are two pinouts for 3d-ram: normal pinout  with pin 1 located at the lower left hand corner and  specially marked by a small circle; and reverse  pinout with pin 1 located at the upper left hand  corner and marked by a large circle and a pointing  triangle. the device in normal pinout is designated  by the letters ?p?in the product number, and the  device in reverse pinout by the letters ?f.? in  both pinouts, the mapping of pin numbers with pin  names is identical. normal pinout diagram scan_tms scan_tck scan_rst vid_q 8 vid_q 9 v ss vid_q 10 vid_q 11 vid_q 12 vid_q 13 v dd vid_q 14 vid_q 15 vid_qsf vid_cke v ss v ss pass_in 0 v dd vid_clk v ss pass_in 1 v ss vid_oe hit vid_q 0 vid_q 1 v dd vid_q 2 vid_q 3 vid_q 4 vid_q 5 v ss vid_q 6 vid_q 7 scan_tdo scan_tdi v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 v dd palu_dq 27 palu_dq 26 palu_dq 25 palu_dq 24 v ss palu_dq 23 palu_dq 22 palu_dq 21 palu_dq 20 v dd palu_dq 19 palu_dq 18 palu_dq 17 palu_dq 16 v ss v ss pass_out v dd mclk nc v ss v ss palu_dq 15 palu_dq 14 palu_dq 13 palu_dq 12 v dd palu_dq 11 palu_dq 10 palu_dq 9 palu_dq 8 v ss palu_dq 7 palu_dq 6 palu_dq 5 palu_dq 4 v dd 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 v dd reset dram_bs 1 dram_bs 0 dram_a 8 dram_a 7 dram_a 6 dram_op 2 dram_op 1 v ss palu_a 5 palu_a 4 palu_a 3 palu_en 1 palu_we palu_op 2 v ss palu_be 3 palu_be 2 palu_dx 3 palu_dx 2 palu_dq 31 palu_dq 30 palu_dq 29 palu_dq 28 v dd 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 m1048 M5M410092Bfp v dd dram_a 0 dram_a 1 dram_a 2 dram_a 3 dram_a 4 dram_a 5 dram_en dram_op 0 v ss palu_a 0 palu_a 1 palu_a 2 palu_en 0 palu_op 0 palu_op 1 v ss palu_be 0 palu_be 1 palu_dx 0 palu_dx 1 palu_dq 0 palu_dq 1 palu_dq 2 palu_dq 3 v dd 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 dddmmmmm-nn

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 138 9 packaging reverse pinout diagram tracking label on the top surface of the 3d-ram package, a  tracking label is printed below the mitsubishi logo  and the 3d-ram product number. the tracking  label consists of 7 numbers followed by a dash  and a speed/power grade designation, and is  represented by the mnemonic ?ddmmmmm-nn?  this mnemonic is explained as below: ddd: date code mmmmm: manufacturing code nn: one of the following speed designations: ?0a  t clk  (min) = 10 ns ?0  t clk  (min) = 10 ns except           tclk (min) = 12 ns for the  alpha saturate logic ?2  t clk  (min) = 12 ns scan_tms scan_tck scan_rst vid_q 8 vid_q 9 v ss vid_q 10 vid_q 11 vid_q 12 vid_q 13 v dd vid_q 14 vid_q 15 vid_qsf vid_cke v ss v ss pass_in 0 v dd vid_clk v ss pass_in 1 v ss vid_oe hit vid_q 0 vid_q 1 v dd vid_q 2 vid_q 3 vid_q 4 vid_q 5 v ss vid_q 6 vid_q 7 scan_tdo scan_tdi v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 v dd palu_dq 27 palu_dq 26 palu_dq 25 palu_dq 24 v ss palu_dq 23 palu_dq 22 palu_dq 21 palu_dq 20 v dd palu_dq 19 palu_dq 18 palu_dq 17 palu_dq 16 v ss v ss pass_out v dd mclk nc v ss v ss palu_dq 15 palu_dq 14 palu_dq 13 palu_dq 12 v dd palu_dq 11 palu_dq 10 palu_dq 9 palu_dq 8 v ss palu_dq 7 palu_dq 6 palu_dq 5 palu_dq 4 v dd 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 v dd reset dram_bs 1 dram_bs 0 dram_a 8 dram_a 7 dram_a 6 dram_op 2 dram_op 1 v ss palu_a 5 palu_a 4 palu_a 3 palu_en 1 palu_we palu_op 2 v ss palu_be 3 palu_be 2 palu_dx 3 palu_dx 2 palu_dq 31 palu_dq 30 palu_dq 29 palu_dq 28 v dd 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 m1003 M5M410092Brf dddmmmmm-nn v dd dram_a 0 dram_a 1 dram_a 2 dram_a 3 dram_a 4 dram_a 5 dram_en dram_op 0 v ss palu_a 0 palu_a 1 palu_a 2 palu_en 0 palu_op 0 palu_op 1 v ss palu_be 0 palu_be 1 palu_dx 0 palu_dx 1 palu_dq 0 palu_dq 1 palu_dq 2 palu_dq 3 v dd 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 139 9 packaging mechanical drawing for 128-pin fp and rf packages     figure 9.1  128-pin fp package drawing l 1 l q detail f m e m d e i 2 b 2 recommended mount pad 1 38 39 64 65 102 103 128 d h d e h e a 2 a 1 a c seating plane eb y seating plane see detail f m1041 m5m410092fp M5M410092Bfp

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 140 9 packaging      figure 9.2  128-pin rf package drawing      l 1 l q detail f m e m d e i 2 b 2 recommended mount pad 102 65 64 39 38 1 128 103 d h d e h e a 2 a 1 a c seating plane eb y seating plane see detail f m1042 M5M410092Brf

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 141 9 packaging table 9.1 package drawing parameters in millimeters symbol dimension in millimeters description min nominal max mounting height a   1.7 stand-off height a 1 0.05 0.15 0.25 package height a 2  1.4  terminal width b 0.13 0.18 0.28 terminal thickness c 0.105 0.125 0.175 package length d 13.9 14.0 14.1 package width e 19.9 20.0 20.1 linear spacing between terminals e  0.5  over length h d 15.8 16.0 16.2 over width h e 21.8 22.0 22.2 length of the ?t portion of terminal l 0.3 0.5 0.7 terminal length l 1  1.0  flatness of terminal y   0.1 terminal angle q 0  ?0  mount pad dimensions b 2  0.225  mount pad dimensions i 2 1.0   mount pad dimensions m d  14.4  mount pad dimensions m e  20.4 

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 142 9 packaging thermal characteristics the maximum junction temperature (t jc ) is set to  125   c. the junction temperature can be  calculated with the following equation: t jc  (  c) =  q ja  (  c/w) x p (w) + t a  (  c) where  q ja  is the junction-to-ambient thermal  resistance, p is the whole chip power dissipation,  and t a  is the ambient temperature. thermal resistance for single package four cases of the thermal resistance for single  package are listed in table 9.2. these four cases  are package only, package on pcb, package on  pcb with thermal compound, and package on  pcb with fin. figures 9.3 through 9.7 show the  detailed conditions of these four cases.           figure 9.3  case 1 condition:  package only        figure 9.4  case 2 condition:  package on pcb        figure 9.5  case 3 condition:  package on pcb with   thermal compound        figure 9.6  case 4 condition:  package on pcb with  ? table 9.2 thermal resistance for single package air?w case 1 package only q ja (  c/w) case 2 package on pcb q ja (  c/w) case 3 package on pcb  with compound q ja (  c/w) case 4 package on pcb with ? q ja (  c/w) 0; or natural convection 160.0 86.0 80.0 44.4 100 ft/min or 0.5 m/s 97.0 66.2 60.3 31.2 200 ft/min or 1.0 m/s 78.0 58.7 53.9 26.3 400 ft/min or 2.0 m/s 59.5 49.4 43.6 20.9 1000 ft/min or 5.0 m/s 43.1 39.5 35.1 16.2 package (adiabatic plane) package (adiabatic plane) pcb package (adiabatic plane) pcb thermal compound package (adiabatic plane) pcb 9.2 mm fin

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 143 9 packaging         figure 9.7  mechanical drawing of the ? f  13 f  6 1.5 1.5 1.0 9.2 2.0 7.5

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 144 9 packaging thermal resistance for twelve packages  mounted on pcb table 9.3 lists the thermal resistance for 12  packages mounted on two sides of a pcb. two  cases are listed: without heat sink and with  aluminum plate for heat sink.              figure 9.8  multiple packages double-side mounted  on pcb, without heat sink        figure 9.9  multiple packages double-side mounted  on pcb, with heat sink table 9.3 thermal resistance for 12 packages  mounting double-sided on pcb air?w without heat  sink q ja (  c/w) with heat  sink q ja (  c/w) 0 m/s or natural  convection 84.0 41.0 100 ft/min or 0.5 m/s 73.0 26.1 200 ft/min or 1.0 m/s 59.2 21.5 400 ft/min or 2.0 m/s 43.8 17.0 1000 ft/min or 5.0 m/s 30.7 13.3 solder pcb fe solder pcb fe resin al plate (40 x 20 x 0.6 mm)

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 145 9 packaging        figure 9.10  mechanical drawing of the mounting, without heat sink 76.2 10.16 air flow 1.6 pcb (glass epoxy)

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 146 9 packaging       figure 9.11  mechanical drawing of the mounting, with heat sink 76.2 10.16 air flow 20 40 1.6 0.6 max  2.5 resin al

 jtag boundary scan 10



 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 147 10 jtag boundary scan jtag boundary scan boundary-scan architecture the 3d-ram provides test features that are  partially in compliance with the ieee standard  1149.1 test access port and boundary-scan  architecture. the on-chip test logic provides a  standardized approach for checking the  interconnections between different components  on the same printed circuit board. the boundary-scan test logic consists of the  boundary-scan register and support logic. the test  function is accessed through the test access port  (tap). the tap provides a simple serial interface  that allows testing of all signal traces with only five  pins in the serial test port. inside the 3d-ram, the boundary-scan cells for  the signal pins are interconnected to form a shift- register chain around the pads. this path has  serial input and output connections with scan  clock and control signals. on a printed circuit  board, the boundary-scan registers for the  individual components can be connected in series  to form a single path through the whole board, as  illustrated in figure 10.1.  alternatively, a board  design could contain several independent  boundary-scan paths. figure 10.1  a boundary-scannable board design boundary-scan cell serial test interconnect system interconnect serial data in serial data out

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 148 10 jtag boundary scan the boundary-scan test logic contains the  following elements: ? test access port (tap), consisting of input  pins scan_tms, scan_tck,  scan_rst and scan_tdi, and an output  pin scan_tdo ? tap controller, which interprets the inputs  on the test mode select line (scan_tms)  and performs the corresponding opera- tions, such as controlling the scan instruc- tion and data registers within the 3d-ram ? instruction register (ir), which accepts  instruction codes shifted through the test  data input (scan_tdi) pin ? two test data registers:  bypass register  (bpr) and boundary-scan register (bsr) the instruction and test data registers are  separate shift-register paths connected in parallel  and have a common serial data input (scan_tdi)  and a common serial data output (scan_tdo).  the data flow is controlled by the tap controller  signals. a block diagram of the boundary-scan  architecture is shown in figure 10.2. figure 10.2  block diagram of the boundary scan architecture scan_tdo boundary scan register bypass register decode instruction register clocks and/or controls tap controller scan_tdi scan_tms scan_tck scan_rst m1002

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 149 10 jtag boundary scan the tap controller the tap controller is a synchronous finite state  machine controlling the sequence of test logic  operations. the tap controller changes state at  the rising edge of the scan_tck pin. the  scan_tms pin controls the sequence of the  state changes. a state diagram for the tap  controller is shown in figure 10.3. the tap controller is initialized either after power  up or when scan_rst is asserted low. in  addition, it can be initialized by applying a high  signal level on the scan_tms input for five  scan_tck cycles. figure 10.3   tap controller state diagram test-logic- reset 0 1 run-test/ idle 0 select- dr-scan 0 1 capture-dr 0 shift-dr 1 0 exit1-dr 0 1 pause-dr 1 0 exit2-dr 1 update-dr 0 1 1 1 0 select- ir-scan 0 1 capture-ir 0 shift-ir 1 0 exit1-ir 0 1 pause-ir 1 0 exit2-ir 1 update-ir 0 1 1 0

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 150 10 jtag boundary scan test-logic-reset state the instruction register is set to the default  bypass instruction, so that normal 3d-ram  operations can proceed without interference. the  tap controller enters this state when it is  initialized after power-up or by the reset signal  scan_rst . regardless of the original state, the  controller enters this state when the scan_tms  input is held high for at least five rising  scan_tck cycles. run-test/idle state this is an idle state. the test data register  selected by the current instruction retains its  previous value during this state. the current  instruction does not change in this state. select-dr-scan state this is a temporary controller state. the test data  register selected by the current instruction retains  its previous value during this state. the current  instruction does not change in this state. capture-dr state the boundary-scan register captures input data  from the scan_tdi pin if the current instruction is  extest or sample/preload. the bypass register  does not change. the current instruction does not  change in this state. shift-dr state the test data register selected by the current  instruction shifts data one stage toward  scan_tdo on each rising edge of scan_tck.  the current instruction does not change in this  state. exit1-dr state this is a temporary controller state. the test data  register selected by the current instruction retains  its previous value during this state. the current  instruction does not change in this state. pause-dr state the pause-dr state allows the data shifting  through the test data register to be temporarily  halted. the test data register selected by the  current instruction retains its previous value during  this state. the current instruction does not change  in this state. exit2-dr state this is a temporary controller state. the test data  register selected by the current instruction retains  its previous value during this state. the current  instruction does not change in this state. update-dr state the boundary-scan cell for output pad has a latch  to prevent changes at the parallel output while  data is shifting along the boundary-scan chain.  when the tap controller is in this state and the  boundary-scan register is selected, data is  latched from the shift-register path on the falling  edge of scan_tck. the data held at the latch  does not change other than in this state. all shift- register stages in selected test data register retain  their previous values during this state. the current  instruction does not change in this state. select-ir-scan state this is a temporary controller state. the test data  register selected by the current instruction retains  its previous state. the current instruction does not  change in this state. capture-ir state the shift-register contained in the instruction  register is loaded with the fixed value ?001?on  the rising edge of scan_tck. the test data  register selected by the current instruction retains  its previous value during this state. the current  instruction does not change in this state. 10 jtag boundary scan

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 151 10 jtag boundary scan shift-ir state the shift-register contained in the instruction  register is connected between the scan_tdi  and scan_tdo pins. the shift-register shifts  data one stage towards its serial output on each  rising edge of scan_tck. the test data register  selected by the current instruction retains its  previous value during this state. the current  instruction does not change in this state. exit1-ir state this is a temporary state. the test data register  selected by the current instruction retains its  previous value during this state. the current  instruction does not change in this state. pause-ir state the pause-ir state allows the data shifting  through the instruction register to be temporarily  halted. the test data register selected by the  current instruction retains its previous value during  this state. the current instruction does not change  in this state. exit2-ir state this is a temporary state. the test data register  selected by the current instruction retains its  previous value during this state. the current  instruction does not change in this state. update-ir state the instruction shifted into the instruction register  is latched from the shift-register path on the falling  edge of scan_tck. the test data register  selected by the current instruction retains its  previous value during this state. once the new  instruction has been latched, it becomes the  current instruction. test data register the 3d-ram contains the two required test data  registers: bypass register and boundary-scan  register. both registers are connected to the  scan_tdi and scan_tdo pins. when a  register is selected by the current instruction, the  data in its shift-register is shifted one stage  towards the scan_tdo output pin on each rising  edge of the scan_tck pin. bypass register the bypass register is a one-bit shift-register that  provides the minimal length path between the  scan_tdi and scan_tdo pins.  when the  3d-ram is not required to perform scan test  operation, this path can be selected to allow rapid  movement of test data to and from other  components on the board. boundary-scan register the boundary-scan register is a shift-register  path containing the boundary-scan cells that are  connected to all input/output signal pins of the  3d-ram except the following pins: mclk,  pass_in [1:0] , pass_out, and vid_clk. the  boundary-scan cells of the palu_dq [31:0]  pins  are implemented as input pins only. figure 10.4  shows the logical structure of the boundary-scan  register. while output cells determine the value of  the signal driven on the corresponding pin, input  cells only capture data. the output cell has a latch  connected to the shift-register for latching the data  in update-dr state. these operations do not  affect the normal operations of the device. data is  shifted from the scan_tdi pin to the scan_tdo  pin through the boundary-scan register during  scanning. the boundary-scan register can be  operated by the extest and sample/preload  instructions.

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 152 10 jtag boundary scan   figure 10.4  logical structure of the boundary-scan register b/s cell reset, palu_dq, palu_dx, palu_a, palu_op, palu_be, palu_en, dram_a, dram_bs, d arm_op, dram_en, vid_cke b/s cell vid_oe b/s cell b/s cell vid_q b/s cell vid_q hit 3d-ram system logic m1001 b/s cell vid_qs f

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 153 10 jtag boundary scan the boundary-scan cells inside the boundary-scan register are organized in the following order: scan_tdi ?  dram_a 0   ?  dram_a 1 ?  dram_a 2 ? dram_a 3 ?  dram_a 4   ?  dram_a 5   ?  dram_en ? dram_op 0 ?  palu_a 0 ?  palu_a 1 ?  palu_a 2 ? palu_en 0 ?  palu_op 0 ?  palu_op 1 ?  palu_be 0 ? palu_be 1 ?  palu_dx 0 ?  palu_dx 1 ?  palu_dq 0 ? palu_dq 1 ?  palu_dq 2 ?  palu_dq 3 ?  palu_dq 4 ? palu_dq 5 ?  palu_dq 6 ?  palu_dq 7 ?  palu_dq 8 ? palu_dq 9 ?  palu_dq 10 ?  palu_dq 11 ?  palu_dq 12 ? palu_dq 13 ?  palu_dq 14 ?  palu_dq 15 ?  palu_dq 16 ? palu_dq 17 ?  palu_dq 18 ?  palu_dq 19 ?  palu_dq 20 ? palu_dq 21 ?  palu_dq 22 ?  palu_dq 23 ?  palu_dq 24 ? palu_dq 25 ?  palu_dq 26 ?  palu_dq 27 ?  palu_dq 28 ? palu_dq 29 ?  palu_dq 30 ?  palu_dq 31 ?  palu_dx 2 ? palu_dx 3 ?  palu_be 2 ?  palu_be 3 ?  palu_op 2 ? palu_we ?  palu_en 1 ?  palu_a 3 ?  palu_a 4 ? palu_a 5 ?  dram_op 1 ?  dram_op 2 ?  dram_a 6 ? dram_a 7 ?  dram_a 8 ?  dram_bs 0 ?  dram_bs 1 ? reset ?  vid_q 8 ?  vid_q 9 ?  vid_q 10 ? vid_q 11 ?  vid_q 12 ?  vid_q 13 ?  vid_q 14 ? vid_q 15 ?  vid_qsf ?  vid_cke ?  vid_oe ? hit ?  vid_q 0 ?  vid_q 1 ?  vid_q 2 ? vid_q 3 ?  vid_q 4 ?  vid_q 5 ?  vid_q 6 ? vid_q 7 ?  scan_tdo instruction register the instruction register (ir) allows instructions to  be serially shifted into the 3d-ram through the  scan_tdi pin. the instruction selects the  particular test to be performed, the test data  register to be accessed, or both. the instruction  register is a four-bit wide shift-register with a  parallel latch. the most significant bit is connected  to the scan_tdi pin and the least significant bit  is connected to the scan_tdo pin. on entering  the capture-ir controller state, the instruction  register is loaded with the default instruction  ?001? which is the bypass instruction.  instructions are shifted into the instruction  register on the rising edge of the scan_tck pin  while the tap controller is in the shift-ir state. the 3d-ram supports all three mandatory  boundary-scan instructions, namely bypass,  sample/preload, and extest. table 10.1 lists the  3d-ram boundary-scan instruction codes.

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 154 10 jtag boundary scan table 10.1  boundary-scan instruction codes bypass instruction the instruction codes for the bypass instruction  are any codes except ?000?(for extest) and  ?100?(for sample/preload). the bypass  instruction selects the bypass register to be  connected to the scan_tdi or scan_tdo pin.  the bypass register contains a single shift- register stage and is used to provide a minimum  length serial path between the scan_tdi and the  scan_tdo pins when no scan test operation of  the 3d-ram is required. this allows more rapid  movement of test data to and from other  components on the board.  due to the pull-up resistor on the scan_tdi  input, an open circuit fault in the board level test  data path will cause the bypass register to be  selected following an instruction scan cycle. this  was done to prevent any unwanted interference  with the normal operation of the 3d-ram. sample/preload instruction the instruction code is ?100? the sample/ preload instruction allows the scanning of the  boundary-scan register without interference to  the normal operation of the 3d-ram. as  suggested by the instruction name, the sample/ preload instruction can be used to perform two  functions:  ? sample is performed in the capture-dr  controller state. all signals received at the  3d-ram input pins are loaded into the  boundary-scan register on the rising edge  of the scan_tck pin. ? preload is performed in the update-dr  controller state. the data held in the shift- register stage of the output cell is latched  on the falling edge of the scan_tck pin. extest instruction the instruction code is ?000? the extest  instruction allows testing of board  interconnections. the extest instruction selects  the boundary-scan register to be connected  between the scan_tdi and scan_tdo pins.  two functions are performed when the extest  instruction is selected: ? in the capture-dr controller state, all sig- nals received at the 3d-ram input pins are  loaded into the boundary-scan register on  the rising edge of the scan_tck pin. this  is equivalent to the sample operation in the  sample/preload instruction. ? in the update-dr controller state, the data  held in the shift-register stage of the output  cell is latched and driven to the 3d-ram  output pins, on the falling edge of the  scan_tck. instruction code instruction name 0000 extest 0001 bypass 0010 bypass 0011 bypass 0100 sample/preload 0101 bypass 0110 bypass 0111 bypass 1000 bypass 1001 bypass 1010 bypass 1011 bypass 1100 bypass 1101 bypass 1110 bypass 1111 bypass

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 155 10 jtag boundary scan vid_oe boundary-scan cell the vid_oe pin controls the tri-state buffer of the  vid_q bus. therefore, its boundary-scan cell  configuration is different from a normal input pin.  the functions performed on this cell for the  sample/preload and extest instructions are  summarized below. ? in the capture-dr controller state, the sig- nal received at the vid_oe pin is loaded  into the shift-register on the rising edge of the  scan_tck pin. ? in the update-dr controller state, the data  held in the shift-register is latched on the  falling edge of the scan_tck pin. if the  instruction is extest, the latched vid_oe  data will control the tri-state buffer of the  vid_q bus.

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 156 10 jtag boundary scan 10 jtag boundary scan

 formal specitcation of operations 11



 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 157 11 formal speci?ation of operations formal speci?ation of operations this chapter specifies exactly which bits are  moved for many types of operations.  it uses a  syntax derived from c and verilog to specify  exactly which bits are copied for each operation. elements bit da[4][257][10240]    dram array bit sa[4][10240] sense amplifiers bit ral[4][9] row address latch bit vb[2][640] video buffer bit vd[16] video data pins bit vc[7] video counter bit vm[1] video mode bit sram[8][256] static ram bit dt[8][32] dirty tag bit pm[32] plane mask register bit dq[32] pixel alu data pins bit be[4] byte enable pins bit daddr[9] dram address bit paddr[6] pixel alu address

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 158 11 formal speci?ation of operations bit ordering of elements     figure 11.1  bit orderings of several elements   0 8 16 24 0 8 16 24 0123 08 0 8 16 24 1 9 17 25 2 101826 3111927 4 122028 5 132129 6 142230 7 152331 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 0816 640 648 656 616 624 632 1256 1264 1272 9576 9584 9592 102161022410232 8960 8968 8976 9600 9608 9616 616 624 632 0816 palu_be pins block palu_dq pins plane mask dirty tags page video buffer vid_q pins

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 159 11 formal speci?ation of operations   figure 11.2 orderings of words and blocks in a page access page access  page(bit bank[2], bit daddr[9]) { bit i[4]; for(i = 0; i < 9; i++) ral[bank][i] <- daddr[i]; bit j[14]; for(j = 0;j < 10240; j++) sa[bank][j] <- da[bank][daddr][j]; } duplicate page duplicate  page(bit bank[2], bit daddr[9]) { bit i[4]; for(i = 0; i < 9; i++) ral[bank][i] <- daddr[i]; bit j[14]; for(j = 0;j < 10240; j++) da[bank][daddr][j] <- sa[bank][j]; } 17 8 162432 4 blocks within a page 5 6 1 2 37 9 10 11 12 13 14 15 0 18 19 20 21 22 23 25 26 27 31 28 29 30 33 34 35 36 37 38 39 0 1 2 3 4 5 6 7 words within a block

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 160 11 formal speci?ation of operations precharge bank precharge(bit bank[2]) {} read block read  block(bit bank[2], bit daddr[9]) { bit i[8]; for(i = 0; i < 256; i++) sram[daddr[8..6]][i] <- sa[bank][daddr[1..0]*2560 + i[7..6]*640 + daddr[5..2]*64 + i[5..0]]; bit j[5]; for(j = 0;j < 32; j++) dt[daddr[8..6]][j] <- 0; } masked write block masked  write  block(bit bank[2], bit daddr[9]) { bit i[8]; for(i = 0; i < 256; i++) if(pm[i[4..0]] && dt[daddr[8..6]][{i[4..3],i[7..5]}]) { sa[bank][daddr[1..0]*2560 + i[7..6]*640 +  daddr[5..2]*64 + i[5..0]] <-  sram[daddr[8..6]][i]; da[bank][ral][daddr[1..0]*2560 + i[7..6]*640 + daddr[5..2]*64 + i[5..0]] <-  sram[daddr[8..6]][i]; } }

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 161 11 formal speci?ation of operations unmasked write block unmasked  write  block(bit bank[2], bit daddr[9]) { bit i[8]; for(i = 0; i < 256; i++) if(dt[daddr[8..6]][{i[4..3],i[7..5]}]) { sa[bank][daddr[1..0]*2560 + i[7..6]*640 +  daddr[5..2]*64 + i[5..0]] <-  sram[daddr[8..6]][i]; da[bank][ral][daddr[1..0]*2560 + i[7..6]*640 + daddr[5..2]*64 + i[5..0]] <-  sram[daddr[8..6]][i]; } } video transfer video  transfer(bit bank[2], bit daddr[9]) { bit i[10]; for(i = 0; i < 640; i++) vb[bank[0]][i] <- sa[bank][640*daddr[3..0] + i]; if(daddr[8]) { vc[5..0] <- 0; vc[6] <- bank[0]; vm[0] <- daddr[7]; } }

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 162 11 formal speci?ation of operations video cycle video  cycle(bit enable[1], bit voe[1]) { if(voe) { bit i[4]; for(i = 0; i < 16; i++) vd[i] <- vb[vc[6]][{vc[5..1],(vc[0]^vm[0])}*16 + i]; } if(enable) { if(vc[5..0] == 39) { vc[5..0] <- 0; vc[6] <- ~vc[6]; } else { vc[5..0] <- vc[5..0] + 1; } } } data read data  read(bit paddr[6]) { bit i[5]; for(i = 0; i < 32; i++) if(be[i[4..3]]) dq[i] <- sram[paddr  [5..3]][paddr[2..0]*32 + i]; }

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 163 11 formal speci?ation of operations stateless initial data write stateless  initial  data  write(bit paddr[6]) { bit i[5]; for(i = 0; i < 32; i++) if(be[i[4..3]]) sram[paddr[5..3]][paddr[2..0]*32 + i] <- dq[i]; bit j[5]; for(j = 0;j < 32; j++) if (cds[0] == 0) /* (8,8,8,8) normal mode */ if((paddr[2..0] == j[2..0]) && be[j[4..3]]) dt[paddr[5..3]][j] <- 1;  else dt[paddr[5..3]][j] <- 0; else /* (4,4,4,4) 16-bit color mode */ if(((be[3] || be[2]) == 1) && ((be[1] || be[0]) == 1)) error(?llegal byte enable combination?; else if((paddr[2..0] == j[2..0]) && j[4]) dt[paddr[5..3]][j] <- (be[3] || be[1]); else if((paddr[2..0] == j[2..0] && !j[4]) dt[paddr[5..3]][j] <- (be[2] || be[0]); else dt[paddr[5..3]][j] <- 0;) }

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 164 11 formal speci?ation of operations stateless normal data write stateless  normal  data  write(bit paddr[6]) { bit i[5]; for(i = 0; i < 32; i++) if(be[i[4..3]]) sram[paddr[5..3]][paddr[2..0]*32 + i] <- dq[i]; bit j[5]; for(j = 0; j < 32; j++) if (cds[0] == 0) /* (8,8,8,8) normal mode */ if((paddr[2..0] == j[2..0]) && be[j[4..3]]) dt[paddr[5..3]][j] <- 1; else /* (4,4,4,4) 16-bit color mode */ if(((be[3] || be[2]) == 1) && ((be[1] || be[0]) == 1)) error(?llegal byte enable combination?; else if((paddr[2..0] == j[2..0]) && j[4]) dt[paddr[5..3]][j] <- (be[3] || be[1]); else if((paddr[2..0] == j[2..0] && !j[4]) dt[paddr[5..3]][j] <- (be[2] || be[0]); } replace dirty tag replace  dirty  tag(bit paddr[6]) { bit i[5]; for(i = 0; i < 32; i++) if(be[i[4..3]]) if (i == paddr[2..0] + 8*i[4..3]) dt[paddr[5..3]][i] <- dq[i]; }

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 165 11 formal speci?ation of operations or dirty tag or  dirty  tag(bit paddr[6]) { bit i[5]; for(i = 0; i < 32; i++) if(be[i[4..3]] && dq[i]) if (i == paddr[2..0] + 8*i[4..3]) dt[paddr[5..3]][i] <- dq[i]; } write plane mask register write  plane  mask  register() { bit i[5]; for(i = 0; i < 32; i++) if(be[i[4..3]]) pm[i] <- dq[i]; }

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 166 11 formal speci?ation of operations

 appendix a 12



 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 167 12 appendix a appendix a glossary some of the terms used in this document may be  unfamiliar to the reader, and some may have a  specific meaning in the context of this document.  for convenience, these terms are collected here  and provided with a brief definition and a  reference to the paragraphs where the terms are  explained in greater detail. this glossary list is not  intended to be exhaustive 3d-ram an innovative 10-mbit cached dual-port cmos  memory device that dramatically improves the  performance of a three-dimensional computer  graphics system with on-chip support for z-buffer  hidden surface removal algorithm and for full  blending and logical raster operations, achieving a  peak bandwidth of 14.6 gbytes/s and a sustained  bandwidth of 400 mbytes/s (for the -10 speed  grade). blending a computer graphics operation for simulating the  visual effect of overlapping objects with the  foreground objects being partially transparent. an  example of blending equations is that overall color  = (a) x (color of foreground object) + (1 - a) x  (color of background object), where a is the  percentage of light transmitted through the  medium of the foreground object. each of the four  8-bit blend units in the pixel alu can perform one  of the two multiplications and then the addition,  provided that the product of the other  multiplication is supplied by the rendering  controller. (pages 10 and 26) block a unit of memory organized into eight 32-bit  words. this is the unit of data movement between  a dram bank and the pixel buffer. (pages 4  and 21) byte a unit of memory containing 8 bits of data. this is  the unit of data operation for the four blend units  in the pixel alu. the rendering controller can  enable or disable the writing (to 3d-ram) or  reading (from 3d-ram) of the individual bytes in a  word. (pages 10, 15, and 26) color buffer the collection of memory that contains all color  bits of all pixels to be displayed on the screen.  because the alpha information is needed for  blending operations in 3d-ram, the alpha data  should also be stored together with the color data.  it is also popular to have overlay information  stored together with the color information to allow  fast display of 2d objects by data multiplexing in a  radmac chip. (chapter 6) dirty tag a 32-bit memory in the pixel buffer, indicating  which of the 32 bytes in the corresponding 256-bit  block in the sram cache have been updated by  the pixel alu since the data was transferred from  the dram array. a ??in a bit of dirty tag  indicates the corresponding byte in the sram  cache is newer than the data in the dram array.  there are eight such dirty tags in the pixel  buffer. (page 22)

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 168 12 appendix a in 2d rendering, this feature may also be used for  color expansion from a bit to a byte to accelerate  drawing of many pixels of the same color. two  pixel alu operations, namely ?eplace dirty  tags?and ?r dirty tags,?may be used to  facilitate this application of the dirty tags.  (page 23) in the (4, 4, 4, 4) 16-bit color mode, the setting of  the dirty tag bits is same as the (8, 8, 8, 8) 32-bit  color mode in the sense that if a byte of data is  updated, then the corresponding dirty tag bit is  set. however, since the palu_be [3:0]  pins have  different meanings in the (4, 4, 4, 4) 16-bit color  mode from the (8, 8, 8, 8) 32-bit color mode, the  specific dirty tag bits that are set are different in  the two color modes. the mapping for the  ?eplace dirty tag?and ?r dirty tag?are the  same in both modes. (page 47) double buffer two color buffers of identical size, with one of  them shifting out video data toward the display  screen (usually through a ramdac chip), while  the other being updated with new pixel data by the  rendering controller. (pages 99 and 101) dram bank one of the four 2.5-mbit dram banks in a  3d-ram chip. each banks has 10,240 sense  amplifiers, which function as a level-two pixel  cache, and 257 pages of 10,240 bits each. all four  dram banks are connected with a common  256-bit global bus to interface with the pixel  buffer. (page 6) frame buffer a collection of memory that contain all bits of data  for all pixels in the display screen and, in some  systems where the frame buffer is large enough to  hold more than the pixel data for the specific  display resolutions, extra pixel data temporarily  stored outside the memory area for display pixels.  a pixel data may include bits for the color value for  each of the r, g, and b color component, bits for  the z (or depth) value, bits for window id, and bits  for some other auxiliary functions, such as  overlay; only the color bits are actually displayed  on the screen, while the other bits are stored with  the color bits for faster graphic processing.  (chapter 6) global bus a 50-mhz (for the -10 speed grade) 256-bit data  bus connecting between the four dram banks  and the pixel buffer. (page 8) magitude compare pixel alu operation that compares the incoming  32-bit data with the 32-bit data stored in the frame  buffer. each bit of the 32-bit magnitude  comparison may be masked by setting a ??in the  corresponding bit of the magnitude mask register.  the result of one of eight possible magnitude  comparison tests can govern whether the new  data is written into the frame buffer. most  commonly, as part of the z-buffer hidden surface  removal algorithm, the magnitude comparison  tests are performed on the z value of the existing  pixel against that of a new pixel intended for the  same screen location. (pages 10, 51 and 61) match compare a pixel alu operation that compares the  incoming 32-bit data with the 32-bit data stored in  the frame buffer. each bit of the 32-bit match  comparison may be masked by setting a ??in the  corresponding bit of the match mask register. the  result of one of four possible match comparison  tests can govern whether the new data is written  into the frame buffer. (pages 10, 51 and 61) page a unit of memory contains forty 256-bit blocks.  three dram operations (pre, acp, and dup)  operate on the entire 10,240-bit page in one  command. (pages 4 and 75)

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 169 12 appendix a picking a computer graphics operation to select a drawn  object on the display screen. a familiar example in  2d graphics is selecting an icon by clicking a  mouse button. in 3d graphics, the selection is  complicated by the z values of objects and the  size and locations (x, y, z) of the 3d selection  cursor, and is supported by the on-chip picking  logic. (pages 12 and 55) picking logic a pixel alu function that provides to the  rendering controller a hit flag, indicating if a pixel  falls within the 3d selection cursor. (pages 12  and 55) pixel alu an on-chip 100-mhz (for the -10 speed grade)  processing unit with a 7-stage pipeline that  performs destination blending/logical raster  operation, magnitude comparison, and match  comparison all in parallel, thus converting the  read-modify-write interface with the rendering  controller to a write-mostly one. (pages 9, 25  and 56) pixel buffer the triple-port 2,048-bit sram as a level-one  pixel cache in 3d-ram with two 100-mhz (for the  -10 speed grade) 32-bit buses interfacing with the  pixel alu and a 50-mhz (for the -10 speed grade)  256-bit bus interfacing with the dram arrays.  also included in the pixel buffer are eight 32-bit  dirty tags and a 32-bit plane mask. (pages 7  and 21) plane mask a 32-bit register that affects both the stateful data  writes to the pixel buffer and the masked block  writes (mbw) to the dram arrays. the effect is  simultaneous on both types of operations when  they are perfomed concurrently by the pixel alu  port and the dram port, respectively. with  respect to the pixel buffer, the plane mask  facilitates the ?rite-per-bit?function on the 32-bit  resultant of the rop/blend units. for mbw, the  effect of the plane mask on the (32-bit) word 0 is  simply extended to words 1 through 7. (pages 23  and 58) rop an abbreviation for raster operation. there is a  total of sixteen standard logical raster operations,  including and, or, and xor. (pages 10, 26  and 60) stateful data write a pixel data operation of the pixel alu. the word  ?tateful?refers to the controls of the dual  compare units and the rop/blend units of the  pixel alu on whether and what data is to be  written into the pixel buffer. there are two types  of stateful data write:  namely, stateful initial  data write and stateful normal data write.  (page 66) stateless data write a pixel data operation of the pixel alu. the word  ?tateless?refers to the straight pass-through of  pixel data from the 3d-ram inputs to the pixel  buffer, with the data write unaffected by the rop/ blend units and the dual compare units of the  pixel alu. there are two types of stateless data  write:  namely, stateless initial data write and  stateless normal data write. (page 72) stencil or stenciling stenciling applies a test that compares a  reference value with the value stored at a pixel in  the stencil buffer and then performs two tasks  based on the results of this stencil test and the  depth test: (1) operates on the update of the  stencil data and (2) controls the write enable of  the color buffer and the depth buffer. the most  common use of stencil function is to generate an  irregular shaped region of some desirable color  pattern, such as a decal. stencil may also be  applied to produce stipples or screened door  patterns which are sometimes employed to  achieve transparency effect without resorting to  the expensive multipliers and adders in the 

 electronic device group m itsubishi  rev. 1.03 3d-ram (M5M410092B) 170 12 appendix a blending function. stencil is also useful in hidden  surface removal. (pages 40 and 66) video buffer one of the two serial access video buffers of  40x16 bits, which alternates every forty vclk  cycles to shift video data out. one video buffer is  connected with two dram banks, and all 640 bits  of a video buffer are loaded by a single dram  command (vdx). the video data output rate is 16  bits per 14-ns cycle. (pages 7 and 78) word a unit of memory representing four bytes. this is  the unit of data movement between the pixel alu  and the pixel buffer. (pages 4 and 21) z buffer the collection of memory that contains all z  values of all pixels to be displayed on the screen.  (pages 99 and 101)